In line with improvements in the degree of element integration or in the reduction in the size of a semiconductor chip in a semiconductor integrated circuit device, miniaturization and multilevel fabrication of interconnects constituting the semiconductor integrated circuit device have been carried out. Particularly, in a logic type semiconductor integrated circuit device having a multilevel interconnect structure, wiring delay is one of the factors which strongly influence the signal delay of the whole semiconductor integrated circuit device. The velocity of a signal which passes through an interconnect strongly depends on the wiring resistance and wiring capacitance, so that a reduction in each of the wiring resistance and the wiring capacitance is important for obtaining an improvement in the wiring delay.
In order to reduce the wiring resistance, a damascene process using a copper-based material (copper or copper alloy) as a wiring material has been employed. In the damascene process, an inlaid interconnect is formed by forming an interconnect-forming trench in an insulating film, adhering an interconnect-forming conductor film both on the insulating film and inside of the interconnect-forming trench, and then removing the unnecessary portion of the conductor film by chemical mechanical polishing (CMP) or the like to leave the conductor film only inside of the trench. This method makes it possible to fabricate an interconnect from a copper-based material which cannot be miniaturized easily by etching.
A dual-damascene process, which is an application of the above-described damascene process, is a method of forming, in an insulating film, an interconnect-forming trench and a hole, such as a contact hole or a through-hole, which extends from the bottom of the trench toward the underlying connecting portion, adhering an interconnect-forming conductor film on the insulating film and inside of the interconnect-forming trench and hole, and removing the unnecessary portion of the conductor film by CMP or the like to leave the conductor film only in the trench and hole, thereby forming an inlaid interconnect in the interconnect-forming trench and a plug in the hole.
An example of such a dual-damascene process is disclosed in Japanese Patent Application Laid-Open No. Hei 9(1997)-306988, wherein an insulating film, which has an opening portion formed for the perforation of a hole and serves as an etching stopper, is disposed between a first interlevel dielectric film and a second interlevel dielectric film laid thereover, and upon formation of a trench in the second interlevel dielectric film by using a photoresist film, the first interlevel dielectric film exposed from the opening portion of the insulating film is perforated with the insulating film as an etching stopper. Another example is disclosed in Japanese Patent Application Laid-Open No. Hei 10(1998)-209273, wherein a trench is formed in an interlevel dielectric film, followed by perforation of a hole extending downwards from the bottom of the trench.
In order to reduce the wiring capacitance, the technique employing as an insulating film, as described above, an organic SOG (Spin On Glass) film, having a methyl group incorporated in a silicon oxide film, can be employed. Owing to a low dielectric constant, this organic SOG film permits lowering of the total dielectric constant of the interconnects of a semiconductor integrated circuit device. A technique using an insulating film having a low dielectric constant as an interlevel dielectric film is described, for example, on pages 74 to 76, “Monthly Semiconductor World, November issue”, published on Oct. 20, 1998 by Press Journal Co., Ltd. This publication discloses various inorganic or organic interlevel dielectric films to be used as an interlevel dielectric film for metallization employing a damascene or dual-damascene process.
Japanese Patent Application Laid-Open No. Hei 9(1997)-293780 discloses a semiconductor integrated circuit devise technique using an organic SOG film as an interlevel dielectric film of the ordinary interconnect structure.
Japanese Patent Application Laid-Open No. Hei 11(1999)-67909 discloses a problem of isotropic etching, in the plane direction, of the side surfaces of a trench or hole upon formation of a trench or hole in an organic low-dielectric-constant film by etching; and a technique is proposed, as a solution of the problem, of employing a foaming gas upon over-etching treatment.
Japanese Patent Application Laid-Open No. Hei 8(1996)-316209 discloses a problem of lowering of the etching rate or deterioration of a processed shape upon etching treatment of an organic polymeric insulating film, which is due to carbon deposits formed on the bottom surface or side surface of a trench or hole made in the organic polymeric insulating film as a result of plasma etching treatment using a CF-based or CHF-based gas similar to that used for etching treatment of a silicon oxide film; and techniques are proposed, as solutions therefor, for conducting plasma etching treatment using an oxygen-based gas upon etching of the organic polymeric insulating film or for conducting plasma etching treatment under the conditions of a lowered C/F ratio in the plasma.
In the above-described damascene or dual-damascene process, an insulating film serving as an etching stopper is formed under the interlevel dielectric film upon formation of an interconnect-forming trench or a hole in the interlevel dielectric film in order to avoid damage to the underlying film by excessive perforation or a deterioration in the processing size accuracy. In the technique for constituting an interlevel dielectric film from silicon oxide or the like, a silicon nitride film is employed as an insulating film serving as an etching stopper. The silicon nitride film has, however, a high dielectric constant (about 7) so that it is necessary to form it as thin as possible from the viewpoint of lowering the total dielectric constant of the interconnects. Upon formation of a trench or hole in an interlevel dielectric film made of silicon oxide or the like, therefore, a technique is employed wherein a CxFy-based gas and oxygen gas are used, thereby carrying out etching under conditions permitting a high etching selectivity to the interlevel dielectric film relative to the insulating film serving as an etching stopper.
The present inventors, however, have found that the formation of a trench or hole by highly-selective etching treatment using, as an etching gas, a CxFy-based gas and O2 gas, is inevitably accompanied by the problem that a trench (sub-trench) relatively deeper than the depth at the bottom center of the trench or hole is formed at the outer periphery of the bottom of the trench or hole. Use of an etching gas having low selectivity to avoid such a problem, however, requires an increase in the thickness of the insulating film serving as an etching stopper, resulting in the problem of an increase in the total dielectric constant of the interconnects of a semiconductor integrated circuit device.
An object of the present invention is, therefore, to provide a technique which is capable of suppressing, upon formation of a recess in an insulating film including an organosiloxane as a main component by etching, the formation of an abnormal shape at the bottom of the recess.
Another object of the present invention is to provide a technique which is capable of suppressing, upon formation of a recess in an insulating film including an organosiloxane as a main component by etching, the formation of an abnormal shape at the bottom of the recess while maintaining a high etching selectivity to the insulating film relative to the etching stopper film.
A further object of the present invention is to provide a technique which is capable of forming a minute recess in an insulating film including an organosiloxane as a main component.
A still further object of the present invention is to provide a technique which is capable of reducing the total dielectric constant of the interconnects of a semiconductor integrated circuit device.
The above-described and the other objects and novel features of the present invention will be apparent from the description herein and the accompanying drawings.